Dynamic memory devices such as DRAM need to be refreshed. This consumes energy. In many systems energy consumption is very crucial for performance, and the power used for refreshing should be reduced.
Energy consumption can be reduced by using a memory that consists not only of a DRAM but also of a less power consuming static memory (SRAM). During standby mode critical data can be stored in the SRAM, and the DRAM can be switched off and not refreshed. Providing an SRAM leads to additional cost and space. Moreover, two different memory access cycles are required.
U.S. Pat. No. 5,331,601 describes a memory device that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.
Another prior art reference, European patent application 488 593, relates to the stability of the refresh in case the power supply fails.
FIG. 1 shows a schematic block diagram of prior art dynamic memory device 101.
Dynamic memory device 101 comprises memory array 110, address generator 112 and decoder 114. The combination of address generator 112 and decoder 114 is referred to as refresh circuit 130. As shown in FIG. 1, dynamic memory device 101 also comprises data terminal 120 and optional terminal 116. Memory array 110 comprises a multitude of storage elements 111 and data accessing means 118. Data accessing means 118 is provided to write, read and update data which is stored in storage elements 111. Data accessing means 118 is connected to storage elements 111 and to data terminal 120.
A physical group of storage elements 111 in memory array 110 is referred to as block 113. Blocks 113 are logically designated by A.sub.1, A.sub.i . . . A.sub.n. In memory array 110, the number of blocks 113 is n. Block addresses a.sub.1, a.sub.i . . . a.sub.n are logically assigned to blocks A.sub.1, A.sub.i . . . A.sub.n. There is one block address a.sub.i for one block A.sub.i.
Outputs 117 of decoder 114 are connected to storage elements 111 of corresponding blocks 113. Address generator 112 is connected to decoder 114 and generates block addresses 119 (a.sub.1, a.sub.i . . . a.sub.n) corresponding to blocks 113 (A.sub.1, A.sub.i . . . A.sub.n).
Dynamic memory device 101 can be connected to other components via data terminal 120 or optional terminal 116. Optional terminal 116 can provide control signal 121 for address generator 112. For example, control signal 121 can be a clock signal.
In one refresh cycle, address generator 112 generates block addresses 119 (a.sub.1, a.sub.i . . . a.sub.n) for all blocks 113 (A.sub.1, A.sub.i . . . A.sub.n) of memory array 110. Block addresses a.sub.1, a.sub.i . . . a.sub.n can have, for example, ascending or descending values. Block addresses a.sub.1, a.sub.i . . . a.sub.n are supplied to decoder 114. Decoder 114 sends refresh signals 115 to corresponding blocks 113 on memory array 110. Upon receiving refresh signal 115 the information of all storage elements 111 of one block 113 is updated by data accessing means 118, thus each block 113 is refreshed. At the end of each refresh cycle, address generator 112 resets automatically and the cycle can start again when a clock signal is available. The clock signal can be supplied as control signal 121 via optional terminal 116. It can also be generated by address generator 112 itself.
It is frequently the case with a DRAM, that data is stored in an array comprising memory cells which are arranged for example in rows. In such a case the memory cells correspond to storage elements 111, the rows to blocks 113, a counter to address generator 112, a row decoder to decoder 114, and data accessing means 118 comprises charge detection circuits for reading the information. Row addresses are generated in the counter and supplied to the row decoder. The row decoder is connected to each row via outputs 117. The signals at the outputs of the row decoder are the above mentioned refresh signals 115. When refresh signal 115 is applied to a particular row, the information of every single memory cell of that particular row is read and the capacitor of that memory cell is recharged if required, thus that row is refreshed.
For convenience of explanation and not intended to be limiting the following example is given:
In a DRAM having an array of 1024.times.1024 memory cells for storing 1 Mbit data, the memory cells are arranged in 1024 rows designated as A.sub.1 . . . A.sub.1024. The row decoder is connected to each row and supplies above mentioned refresh signals 115 to the rows. The counter produces increasing addresses a.sub.i which are integer numbers from a.sub.1 =1 to a.sub.1024 =1024. When, for example, the address a.sub.256 =256 is supplied to the input of the row decoder then all 1024 memory cells of row A.sub.256 are refreshed one after another. The charge of each memory cell is detected by a charge detection circuit which is part of data accessing means 118. If the memory cell is charged, than it is recharged. That means that all memory cells with charged capacitors (e.g., representing the bit "1") are recharged, and these with uncharged capacitors (e.g., representing the bit "0") are not recharged.
A DRAM usually also includes data accessing means 118 to read the information of each memory cell. Additional addresses such as, for example, column addresses are required to access each memory cell. That additional addresses can be supplied via data terminal 120.
In dynamic memory device 101 of FIG. 1, all blocks 113 of memory array 110 are refreshed in every refresh cycle, thus consuming energy.
The invention provides an improved refresh circuit for dynamic memory devices and a method for refreshing such devices that reduces or overcomes the above mentioned problems of prior art.